253 lines
6.8 KiB
C
253 lines
6.8 KiB
C
/* ------------------------------------------------------------------
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* Copyright (C) 1998-2009 PacketVideo
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
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* express or implied.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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* -------------------------------------------------------------------
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*/
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/*
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------------------------------------------------------------------------------
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PacketVideo Corp.
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MP3 Decoder Library
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Pathname: ./cpp/include/pv_mp3dec_fxd_op_arm_gcc.h
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Date: 08/20/2007
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------------------------------------------------------------------------------
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REVISION HISTORY
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Description:
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------------------------------------------------------------------------------
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INCLUDE DESCRIPTION
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This file select the associated fixed point functions with the OS/ARCH.
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------------------------------------------------------------------------------
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*/
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#ifndef PV_MP3DEC_FXD_OP_ARM_GCC_H
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#define PV_MP3DEC_FXD_OP_ARM_GCC_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "pvmp3_audio_type_defs.h"
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#if (defined(PV_ARM_GCC_V5)||defined(PV_ARM_GCC_V4))
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#define Qfmt_31(a) (int32)(a*0x7FFFFFFF + (a>=0?0.5F:-0.5F))
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#define Qfmt15(x) (Int16)(x*((int32)1<<15) + (x>=0?0.5F:-0.5F))
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static inline int32 fxp_mul32_Q30(const int32 a, const int32 b)
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{
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int32 result64_hi;
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int32 result64_lo;
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register int32 ra = (int32)a;
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register int32 rb = (int32)b;
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asm volatile("smull %1, %0, %2, %3\n\t"
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"mov %1, %1, lsr #30\n\t"
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"add %0, %1, %0, asl #2"
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: "=&r*i"(result64_hi),
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"=&r*i"(result64_lo)
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: "r"(ra),
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"r"(rb));
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return (result64_hi);
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}
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static inline int32 fxp_mac32_Q30(const int32 a, const int32 b, int32 L_add)
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{
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int32 result64_hi;
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int32 result64_lo;
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register int32 ra = (int32)a;
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register int32 rb = (int32)b;
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register int32 rc = (int32)L_add;
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asm volatile("smull %1, %0, %2, %3\n\t"
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"add %4, %4, %0, asl #2\n\t"
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"add %0, %4, %1, lsr #30"
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: "=&r*i"(result64_hi),
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"=&r*i"(result64_lo)
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: "r"(ra),
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"r"(rb),
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"r"(rc));
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return (result64_hi);
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}
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static inline int32 fxp_mul32_Q32(const int32 a, const int32 b)
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{
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int32 result64_hi;
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int32 result64_lo;
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register int32 ra = (int32)a;
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register int32 rb = (int32)b;
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asm volatile(
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"smull %1, %0, %2, %3"
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: "=&r*i"(result64_hi),
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"=&r*i"(result64_lo)
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: "r"(ra),
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"r"(rb));
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return (result64_hi);
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}
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static inline int32 fxp_mul32_Q29(const int32 a, const int32 b)
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{
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int32 result64_hi;
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int32 result64_lo;
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register int32 ra = (int32)a;
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register int32 rb = (int32)b;
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asm volatile("smull %1, %0, %2, %3\n\t"
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"mov %1, %1, lsr #29\n\t"
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"add %0, %1, %0, asl #3"
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: "=&r*i"(result64_hi),
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"=&r*i"(result64_lo)
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: "r"(ra),
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"r"(rb));
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return (result64_hi);
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}
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static inline int32 fxp_mul32_Q28(const int32 a, const int32 b)
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{
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int32 result64_hi;
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int32 result64_lo;
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register int32 ra = (int32)a;
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register int32 rb = (int32)b;
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asm volatile("smull %1, %0, %2, %3\n\t"
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"mov %1, %1, lsr #28\n\t"
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"add %0, %1, %0, asl #4"
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: "=&r*i"(result64_hi),
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"=&r*i"(result64_lo)
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: "r"(ra),
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"r"(rb));
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return (result64_hi);
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}
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static inline int32 fxp_mul32_Q27(const int32 a, const int32 b)
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{
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int32 result64_hi;
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int32 result64_lo;
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register int32 ra = (int32)a;
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register int32 rb = (int32)b;
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asm volatile("smull %1, %0, %2, %3\n\t"
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"mov %1, %1, lsr #27\n\t"
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"add %0, %1, %0, asl #5"
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: "=&r*i"(result64_hi),
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"=&r*i"(result64_lo)
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: "r"(ra),
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"r"(rb));
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return (result64_hi);
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}
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static inline int32 fxp_mul32_Q26(const int32 a, const int32 b)
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{
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int32 result64_hi;
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int32 result64_lo;
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register int32 ra = (int32)a;
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register int32 rb = (int32)b;
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asm volatile("smull %1, %0, %2, %3\n\t"
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"mov %1, %1, lsr #26\n\t"
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"add %0, %1, %0, asl #6"
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: "=&r*i"(result64_hi),
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"=&r*i"(result64_lo)
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: "r"(ra),
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"r"(rb));
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return (result64_hi);
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}
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static inline int32 fxp_mac32_Q32(int32 L_add, const int32 a, const int32 b)
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{
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int32 result64_hi;
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int32 result64_lo;
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register int32 ra = (int32)a;
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register int32 rb = (int32)b;
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register int32 rc = (int32)L_add;
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asm volatile("smull %1, %0, %2, %3\n\t"
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"add %0, %0, %4"
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: "=&r*i"(result64_hi),
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"=&r*i"(result64_lo)
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: "r"(ra),
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"r"(rb),
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"r"(rc));
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return (result64_hi);
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}
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static inline int32 fxp_msb32_Q32(int32 L_sub, const int32 a, const int32 b)
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{
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int32 result64_hi;
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int32 result64_lo;
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register int32 ra = (int32)a;
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register int32 rb = (int32)b;
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register int32 rc = (int32)L_sub;
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asm volatile("smull %1, %0, %2, %3\n\t"
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"sub %0, %4, %0"
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: "=&r*i"(result64_hi),
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"=&r*i"(result64_lo)
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: "r"(ra),
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"r"(rb),
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"r"(rc));
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return (result64_hi);
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}
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__inline int32 pv_abs(int32 x)
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{
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register int32 z;
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register int32 y;
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register int32 ra = x;
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asm volatile(
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"sub %0, %2, %2, lsr #31\n\t"
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"eor %1, %0, %0, asr #31"
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: "=&r*i"(z),
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"=&r*i"(y)
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: "r"(ra));
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return (y);
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* PV_MP3DEC_FXD_OP_ARM_GCC_H */
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